Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt Opamp1_Pin_3 gnda vdda vinn vinp vout
xm6 net11 vb1 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm5 vout vb2 vdda vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm1 net16 vinn net11 vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm0 net9 vinp net11 vdda sky130_fd_pr__pfet_01v8 l='P4_L' w='P4_W*1' m='P4_M'
xm4 vout net16 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm3 net16 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm2 net9 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
C0 vout net16 'CAPACITOR_0'
V1 vb1 0 'VB1'
V2 vb2 0 'VB2'
.ends Opamp1_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_P4:
    min: 0.13
    max: 1.0
    type: real
  W_P4:
    min: 0.2
    max: 10.0
    type: real
  M_P4:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  V2:
    min: 0.0
    max: 1.8
    type: real
Here is the design target
PSRP_target = -65          # dB
PSRN_target = -80          # dB
TC_target = 5e-5           # 50 ppm/°C
Power_target = 3e-4        # W (0.3 mW @ 1.8 V)
vos_target = 1e-3          # V (1 mV)
cmrrdc_target = -70        # dB
dcgain_target = 80         # dB
GBW_target = 3e6           # Hz
phase_margin_target = 60   # deg
sr_target = 1e6            # V/s (≈1 V/µs)
settlingTime_target = 2e-6 # s
Provide your design parameter in this format
parameters:
  L_P1: 
  W_P1: 
  M_P1: 
  L_P2: 
  W_P2: 
  M_P2: 
  L_P3: 
  W_P3: 
  M_P3: 
  L_P4: 
  W_P4: 
  M_P4: 
  L_N1: 
  W_N1: 
  M_N1: 
  L_N2: 
  W_N2: 
  M_N2: 
  L_N3: 
  W_N3: 
  M_N3: 
  C0: 
  V1: 
  V2: 