Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP10_Pin_3 gnda vdda vinn vinp vout
xm12 vout vb1 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm4 net20 net26 net32 vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm3 net10 net26 net33 vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm2 net26 net26 ib1 vdda sky130_fd_pr__pfet_01v8 l='P4_L' w='P4_W*1' m='P4_M'
xm1 net32 vinn ib1 vdda sky130_fd_pr__pfet_01v8 l='P5_L' w='P5_W*1' m='P5_M'
xm0 net33 vinp ib1 vdda sky130_fd_pr__pfet_01v8 l='P6_L' w='P6_W*1' m='P6_M'
xm11 vout net22 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm10 net22 net15 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm9 vdda net20 net22 gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm8 net15 net15 gnda gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
xm7 net31 net15 gnda gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
xm6 net20 net10 net15 gnda sky130_fd_pr__nfet_01v8 l='N6_L' w='N6_W*1' m='N6_M'
xm5 net10 net10 net31 gnda sky130_fd_pr__nfet_01v8 l='N7_L' w='N7_W*1' m='N7_M'
C0 vout net30 'CAPACITOR_0'
R0 net30 net20 'RESISTOR_0'
V1 vb1 0 'VB1'
I0 vdda ib1 'IB1'
.ends OPAMP10_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_P4:
    min: 0.13
    max: 1.0
    type: real
  W_P4:
    min: 0.2
    max: 10.0
    type: real
  M_P4:
    min: 1
    max: 100
    type: int
  L_P5:
    min: 0.13
    max: 1.0
    type: real
  W_P5:
    min: 0.2
    max: 10.0
    type: real
  M_P5:
    min: 1
    max: 100
    type: int
  L_P6:
    min: 0.13
    max: 1.0
    type: real
  W_P6:
    min: 0.2
    max: 10.0
    type: real
  M_P6:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  L_N5:
    min: 0.13
    max: 1.0
    type: real
  W_N5:
    min: 0.2
    max: 10.0
    type: real
  M_N5:
    min: 1
    max: 100
    type: int
  L_N6:
    min: 0.13
    max: 1.0
    type: real
  W_N6:
    min: 0.2
    max: 10.0
    type: real
  M_N6:
    min: 1
    max: 100
    type: int
  L_N7:
    min: 0.13
    max: 1.0
    type: real
  W_N7:
    min: 0.2
    max: 10.0
    type: real
  M_N7:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  R0:
    min: 0.1
    max: 1000.0
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  Ib1:
    min: 1e-6
    max: 4e-5
    type: real
Here is the design target
PSRP_target = -75          # dB  @1 kHz (from VDD)
PSRN_target = -92          # dB  @1 kHz (from VSS)
TC_target = 2e-5           # 20 ppm/°C (gain/offset drift)
Power_target = 3e-4        # W  ≈0.30 mW
vos_target = 5e-4          # V  ≈0.5 mV
cmrrdc_target = -85        # dB
dcgain_target = 100        # dB
GBW_target = 1.2e7         # Hz  (~12 MHz with 10 pF)
phase_margin_target = 60   # deg
sr_target = 1.2e7          # V/s  ≈12 V/µs
settlingTime_target = 6e-7 # s  (~0.1–0.5% to 10 pF)
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_P4:
  W_P4:
  M_P4:
  L_P5:
  W_P5:
  M_P5:
  L_P6:
  W_P6:
  M_P6:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  L_N5:
  W_N5:
  M_N5:
  L_N6:
  W_N6:
  M_N6:
  L_N7:
  W_N7:
  M_N7:
  C0:
  R0:
  V1:
  Ib1: