Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP11_Pin_3 gnda vdda vinn vinp vout
xm26 vout net074 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm23 net036 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm20 net031 net031 vdda vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm19 net030 net030 net031 vdda sky130_fd_pr__pfet_01v8 l='P4_L' w='P4_W*1' m='P4_M'
xm0 net081 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P5_L' w='P5_W*1' m='P5_M'
xm1 net082 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P6_L' w='P6_W*1' m='P6_M'
xm2 ib1 ib1 net081 vdda sky130_fd_pr__pfet_01v8 l='P7_L' w='P7_W*1' m='P7_M'
xm3 net066 ib1 net082 vdda sky130_fd_pr__pfet_01v8 l='P8_L' w='P8_W*1' m='P8_M'
xm4 net085 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P9_L' w='P9_W*1' m='P9_M'
xm5 net078 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P10_L' w='P10_W*1' m='P10_M'
xm18 net038 net030 net074 vdda sky130_fd_pr__pfet_01v8 l='P11_L' w='P11_W*1' m='P11_M'
xm7 net074 ib1 net078 vdda sky130_fd_pr__pfet_01v8 l='P12_L' w='P12_W*1' m='P12_M'
xm6 net071 ib1 net085 vdda sky130_fd_pr__pfet_01v8 l='P13_L' w='P13_W*1' m='P13_M'
xm27 vout net038 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm25 net036 net036 net87 gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm24 net87 net87 gnda gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm22 net074 net036 net038 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
xm21 net030 net011 gnda gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
xm8 net056 net071 gnda gnda sky130_fd_pr__nfet_01v8 l='N6_L' w='N6_W*1' m='N6_M'
xm17 net055 net071 gnda gnda sky130_fd_pr__nfet_01v8 l='N7_L' w='N7_W*1' m='N7_M'
xm16 net071 net071 net055 gnda sky130_fd_pr__nfet_01v8 l='N8_L' w='N8_W*1' m='N8_M'
xm15 net038 net071 net056 gnda sky130_fd_pr__nfet_01v8 l='N9_L' w='N9_W*1' m='N9_M'
xm14 net078 vinp net069 gnda sky130_fd_pr__nfet_01v8 l='N10_L' w='N10_W*1' m='N10_M'
xm13 ib1 vinn net069 gnda sky130_fd_pr__nfet_01v8 l='N11_L' w='N11_W*1' m='N11_M'
xm9 net084 net011 gnda gnda sky130_fd_pr__nfet_01v8 l='N12_L' w='N12_W*1' m='N12_M'
xm12 net011 net066 net083 gnda sky130_fd_pr__nfet_01v8 l='N13_L' w='N13_W*1' m='N13_M'
xm11 net069 net066 net084 gnda sky130_fd_pr__nfet_01v8 l='N14_L' w='N14_W*1' m='N14_M'
xm10 net083 net011 gnda gnda sky130_fd_pr__nfet_01v8 l='N15_L' w='N15_W*1' m='N15_M'
C1 vout net038 'CAPACITOR_1'
C0 net074 vout 'CAPACITOR_0'
R0 net066 net011 'RESISTOR_0'
I0 ib1 gnda 'IB1'
.ends OPAMP11_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_P4:
    min: 0.13
    max: 1.0
    type: real
  W_P4:
    min: 0.2
    max: 10.0
    type: real
  M_P4:
    min: 1
    max: 100
    type: int
  L_P5:
    min: 0.13
    max: 1.0
    type: real
  W_P5:
    min: 0.2
    max: 10.0
    type: real
  M_P5:
    min: 1
    max: 100
    type: int
  L_P6:
    min: 0.13
    max: 1.0
    type: real
  W_P6:
    min: 0.2
    max: 10.0
    type: real
  M_P6:
    min: 1
    max: 100
    type: int
  L_P7:
    min: 0.13
    max: 1.0
    type: real
  W_P7:
    min: 0.2
    max: 10.0
    type: real
  M_P7:
    min: 1
    max: 100
    type: int
  L_P8:
    min: 0.13
    max: 1.0
    type: real
  W_P8:
    min: 0.2
    max: 10.0
    type: real
  M_P8:
    min: 1
    max: 100
    type: int
  L_P9:
    min: 0.13
    max: 1.0
    type: real
  W_P9:
    min: 0.2
    max: 10.0
    type: real
  M_P9:
    min: 1
    max: 100
    type: int
  L_P10:
    min: 0.13
    max: 1.0
    type: real
  W_P10:
    min: 0.2
    max: 10.0
    type: real
  M_P10:
    min: 1
    max: 100
    type: int
  L_P11:
    min: 0.13
    max: 1.0
    type: real
  W_P11:
    min: 0.2
    max: 10.0
    type: real
  M_P11:
    min: 1
    max: 100
    type: int
  L_P12:
    min: 0.13
    max: 1.0
    type: real
  W_P12:
    min: 0.2
    max: 10.0
    type: real
  M_P12:
    min: 1
    max: 100
    type: int
  L_P13:
    min: 0.13
    max: 1.0
    type: real
  W_P13:
    min: 0.2
    max: 10.0
    type: real
  M_P13:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  L_N5:
    min: 0.13
    max: 1.0
    type: real
  W_N5:
    min: 0.2
    max: 10.0
    type: real
  M_N5:
    min: 1
    max: 100
    type: int
  L_N6:
    min: 0.13
    max: 1.0
    type: real
  W_N6:
    min: 0.2
    max: 10.0
    type: real
  M_N6:
    min: 1
    max: 100
    type: int
  L_N7:
    min: 0.13
    max: 1.0
    type: real
  W_N7:
    min: 0.2
    max: 10.0
    type: real
  M_N7:
    min: 1
    max: 100
    type: int
  L_N8:
    min: 0.13
    max: 1.0
    type: real
  W_N8:
    min: 0.2
    max: 10.0
    type: real
  M_N8:
    min: 1
    max: 100
    type: int
  L_N9:
    min: 0.13
    max: 1.0
    type: real
  W_N9:
    min: 0.2
    max: 10.0
    type: real
  M_N9:
    min: 1
    max: 100
    type: int
  L_N10:
    min: 0.13
    max: 1.0
    type: real
  W_N10:
    min: 0.2
    max: 10.0
    type: real
  M_N10:
    min: 1
    max: 100
    type: int
  L_N11:
    min: 0.13
    max: 1.0
    type: real
  W_N11:
    min: 0.2
    max: 10.0
    type: real
  M_N11:
    min: 1
    max: 100
    type: int
  L_N12:
    min: 0.13
    max: 1.0
    type: real
  W_N12:
    min: 0.2
    max: 10.0
    type: real
  M_N12:
    min: 1
    max: 100
    type: int
  L_N13:
    min: 0.13
    max: 1.0
    type: real
  W_N13:
    min: 0.2
    max: 10.0
    type: real
  M_N13:
    min: 1
    max: 100
    type: int
  L_N14:
    min: 0.13
    max: 1.0
    type: real
  W_N14:    
    min: 0.2
    max: 10.0
    type: real
  M_N14:
    min: 1
    max: 100
    type: int
  L_N15:
    min: 0.13
    max: 1.0
    type: real
  W_N15:
    min: 0.2
    max: 10.0
    type: real
  M_N15:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  C1:
    min: 1.0
    max: 100.0
    type: real
  R0:
    min: 0.1
    max: 1000.0
    type: real
  Ib1:
    min: 1e-6
    max: 4e-5
    type: real
Here is the design target
PSRP_target = -82          # dB @1 kHz (from VDD)
PSRN_target = -100         # dB @1 kHz (from VSS)
TC_target = 2e-5           # 20 ppm/°C (gain/offset drift)
Power_target = 3.5e-4      # W  ≈0.35 mW
vos_target = 3e-4          # V  ≈0.3 mV
cmrrdc_target = -90        # dB
dcgain_target = 108        # dB
GBW_target = 1.5e7         # Hz  (~15 MHz with 10 pF)
phase_margin_target = 65   # deg
sr_target = 2.0e7          # V/s  ≈20 V/µs
settlingTime_target = 5e-7 # s  (≈0.1–0.5% to 10 pF)
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_P4:
  W_P4:
  M_P4:
  L_P5:
  W_P5:
  M_P5:
  L_P6:
  W_P6:
  M_P6:
  L_P7:
  W_P7:
  M_P7:
  L_P8:
  W_P8:
  M_P8:
  L_P9:
  W_P9:
  M_P9:
  L_P10:
  W_P10:
  M_P10:
  L_P11:
  W_P11:
  M_P11:
  L_P12:
  W_P12:
  M_P12:
  L_P13:
  W_P13:
  M_P13:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  L_N5:
  W_N5:
  M_N5:
  L_N6:
  W_N6:
  M_N6:
  L_N7:
  W_N7:
  M_N7:
  L_N8:
  W_N8:
  M_N8:
  L_N9:
  W_N9:
  M_N9:
  L_N10:
  W_N10:
  M_N10:
  L_N11:
  W_N11:
  M_N11:
  L_N12:
  W_N12:
  M_N12:
  L_N13:
  W_N13:
  M_N13:
  L_N14:
  W_N14:    
  M_N14:
  L_N15:
  W_N15:
  M_N15:
  C0:
  C1:
  R0:
  Ib1: