Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP17_Pin_3 gnda vdda vinn vinp vout
xm6 vout net34 net35 vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm5 net34 net34 net18 vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm4 net18 net18 vdda vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm3 net35 net18 vdda vdda sky130_fd_pr__pfet_01v8 l='P4_L' w='P4_W*1' m='P4_M'
xm2 net27 vinn net9 vdda sky130_fd_pr__pfet_01v8 l='P5_L' w='P5_W*1' m='P5_M'
xm1 net24 vinp net9 vdda sky130_fd_pr__pfet_01v8 l='P6_L' w='P6_W*1' m='P6_M'
xm0 net9 vb1 vdda vdda sky130_fd_pr__pfet_01v8 l='P7_L' w='P7_W*1' m='P7_M'
xm10 net27 vb3 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm9 net24 vb3 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm8 vout vb2 net27 gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm7 net34 vb2 net24 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
C0 vout gnda 'CAPACITOR_0'
V0 vb1 gnda 'VB1'
V1 vb2 gnda 'VB2'
V2 vb3 gnda 'VB3'
.ends OPAMP17_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_P4:
    min: 0.13
    max: 1.0
    type: real
  W_P4:
    min: 0.2
    max: 10.0
    type: real
  M_P4:
    min: 1
    max: 100
    type: int
  L_P5:
    min: 0.13
    max: 1.0
    type: real
  W_P5:
    min: 0.2
    max: 10.0
    type: real
  M_P5:
    min: 1
    max: 100
    type: int
  L_P6:
    min: 0.13
    max: 1.0
    type: real
  W_P6:
    min: 0.2
    max: 10.0
    type: real
  M_P6:
    min: 1
    max: 100
    type: int
  L_P7:
    min: 0.13
    max: 1.0
    type: real
  W_P7:
    min: 0.2
    max: 10.0
    type: real
  M_P7:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  V2:
    min: 0.0
    max: 1.8
    type: real
  V3:
    min: 0.0
    max: 1.8
    type: real
Here is the design target
PSRP_target = -75          # dB @1 kHz (from VDD)
PSRN_target = -95          # dB @1 kHz (from VSS)
TC_target = 3e-5           # 30 ppm/°C
Power_target = 2.5e-4      # W  (~0.25 mW)
vos_target = 7e-4          # V  (~0.7 mV)
cmrrdc_target = -82        # dB
dcgain_target = 90         # dB
GBW_target = 1.1e7         # Hz
phase_margin_target = 60   # deg
sr_target = 1.0e7          # V/s  (~10 V/µs)
settlingTime_target = 8e-7 # s to ~0.1–0.5% on 10 pF
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_P4:
  W_P4:
  M_P4:
  L_P5:
  W_P5:
  M_P5:
  L_P6:
  W_P6:
  M_P6:
  L_P7:
  W_P7:
  M_P7:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  C0:
  V1:
  V2:
  V3: