Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP2_Pin_3 gnda vdda vinn vinp vout
xm8 net36 vb2 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm7 net30 vb1 vdda vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm5 vout vb4 vdda vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm6 net33 vb3 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm1 net36 vinn net33 gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm0 net30 vinp net33 gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm4 vout net36 gnda gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
xm3 net36 net30 gnda gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
xm2 net30 net30 gnda gnda sky130_fd_pr__nfet_01v8 l='N6_L' w='N6_W*1' m='N6_M'
C0 vout net36 'CAPACITOR_0'
V1 vb1 0 'VB1'
V2 vb2 0 'VB2'
V3 vb3 0 'VB3'
V4 vb4 0 'VB4'
.ends OPAMP2_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  L_N5:
    min: 0.13
    max: 1.0
    type: real
  W_N5:
    min: 0.2
    max: 10.0
    type: real
  M_N5:
    min: 1
    max: 100
    type: int
  L_N6:
    min: 0.13
    max: 1.0
    type: real
  W_N6:
    min: 0.2
    max: 10.0
    type: real
  M_N6:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  V2:
    min: 0.0
    max: 1.8
    type: real
  V3:
    min: 0.0
    max: 1.8
    type: real
  V4:
    min: 0.0
    max: 1.8
    type: real
Here is the design target
PSRP_target = -70          # dB  (from VDD @1 kHz)
PSRN_target = -85          # dB  (from VSS @1 kHz)
TC_target = 2e-5           # 20 ppm/°C (gain/offset drift)
Power_target = 3e-4        # W  ≈0.3 mW
vos_target = 5e-4          # V  ≈0.5 mV (good layout)
cmrrdc_target = -75        # dB
dcgain_target = 85         # dB
GBW_target = 4e6           # Hz  (with CL≈10 pF)
phase_margin_target = 60   # deg
sr_target = 2e6            # V/s ≈2 V/µs (class-A-ish output)
settlingTime_target = 1.5e-6  # s to ~0.1–0.5% on 10 pF
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  L_N5:
  W_N5:
  M_N5:
  L_N6:
  W_N6:
  M_N6:
  C0:
  V1:
  V2:
  V3:
  V4: