Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP20_Pin_3 gnda vdda vinn vinp vout
xm1 net15 vinp ib1 vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm0 net9 vinn ib1 vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm6 vout net15 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm5 net14 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm4 net19 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm3 net15 vb1 net14 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
xm2 net9 vb1 net19 gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
C0 vout net14 'CAPACITOR_0'
R0 vdda vout 'RESISTOR_0'
V0 vb1 gnda 'VB1'
I0 vdda ib1 'IB1'
.ends OPAMP20_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  L_N5:
    min: 0.13
    max: 1.0
    type: real
  W_N5:
    min: 0.2
    max: 10.0
    type: real
  M_N5:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  R0:
    min: 0.1
    max: 1000.0
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  Ib1:
    min: 1e-6
    max: 4e-5
    type: real
Here is the design target
PSRP_target = -76          # dB  (from VDD @ 1 kHz)
PSRN_target = -95          # dB  (from VSS @ 1 kHz)
TC_target   = 2e-5         # 20 ppm/°C
Power_target = 3.0e-4      # W  ≈0.30 mW
vos_target   = 5e-4        # V  ≈0.5 mV
cmrrdc_target = -88        # dB
dcgain_target = 100        # dB
GBW_target   = 1.6e7       # Hz  (~16 MHz with CL≈10 pF)
phase_margin_target = 65   # deg
sr_target    = 2.2e7       # V/s  ≈22 V/µs
settlingTime_target = 4.8e-7  # s (≈0.1–0.5% to 10 pF)
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  L_N5:
  W_N5:
  M_N5:
  C0:
  R0:
  V1:
  Ib1: