Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP5_Pin_3 gnda vdda vinn vinp vout
xm8 vout vb2 net018 vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm6 net017 net017 vdda vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm7 net018 net017 vdda vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm5 net016 vinp ib1 gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm4 net017 vb1 net016 gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm1 vout vb1 net019 gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm3 net019 vinn ib1 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
C0 vout gnda 'CAPACITOR_0'
V1 vb1 0 'VB1'
V2 vb2 0 'VB2'
I0 ib1 gnda 'IB1'
.ends OPAMP5_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  Ib1:
    min: 1e-6
    max: 4e-5
    type: real
  V1:
    min: 0.0
    max: 1.8
    type: real
  V2:
    min: 0.0
    max: 1.8
    type: real
Here is the design target
PSRP_target = -65          # dB @1 kHz (from VDD)
PSRN_target = -88          # dB @1 kHz (from VSS)
TC_target   = 3e-5         # 30 ppm/°C (gain/offset drift)
Power_target= 2.5e-4       # W  ≈0.25 mW
vos_target  = 7e-4         # V  ≈0.7 mV
cmrrdc_target = -78        # dB
dcgain_target = 85         # dB
GBW_target  = 1e7          # Hz  (≈10 MHz with CL≈10 pF)
phase_margin_target = 60   # deg
sr_target   = 8e6          # V/s  ≈8 V/µs (SRE path)
settlingTime_target = 9e-7 # s to ~0.1–0.5% on 10 pF
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  C0:
  Ib1:
  V1:
  V2: