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-- distribute this software, either in source code form or as a compiled
-- binary, for any purpose, commercial or non-commercial, and by any
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-- of this software dedicate any and all copyright interest in the
-- software to the public domain. We make this dedication for the benefit
-- of the public at large and to the detriment of our heirs and
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library ieee;
use ieee.std_logic_1164.all;


entity rom_128x10_exclif4 is
    port (
        clka : in std_logic;
        addra : in std_logic_vector(6 downto 0);
        dout_0 : out std_logic_vector(7 downto 0);
        dout_1 : out std_logic_vector(7 downto 0);
        dout_2 : out std_logic_vector(7 downto 0);
        dout_3 : out std_logic_vector(7 downto 0);
        dout_4 : out std_logic_vector(7 downto 0);
        dout_5 : out std_logic_vector(7 downto 0);
        dout_6 : out std_logic_vector(7 downto 0);
        dout_7 : out std_logic_vector(7 downto 0);
        dout_8 : out std_logic_vector(7 downto 0);
        dout_9 : out std_logic_vector(7 downto 0)
    );
end entity rom_128x10_exclif4;

architecture behavior of rom_128x10_exclif4 is


    component rom_128x10_exclif4_ip is
        port (
            clka : in std_logic;
            addra : in std_logic_vector(6 downto 0);
            douta : out std_logic_vector(79 downto 0)
        );
    end component;


    signal douta : std_logic_vector(79 downto 0);

begin

    dout_0 <= douta(7 downto 0);
    dout_1 <= douta(15 downto 8);
    dout_2 <= douta(23 downto 16);
    dout_3 <= douta(31 downto 24);
    dout_4 <= douta(39 downto 32);
    dout_5 <= douta(47 downto 40);
    dout_6 <= douta(55 downto 48);
    dout_7 <= douta(63 downto 56);
    dout_8 <= douta(71 downto 64);
    dout_9 <= douta(79 downto 72);


    rom_128x10_exclif4_ip_instance : rom_128x10_exclif4_ip
        port map(
            clka => clka,
            addra => addra,
            douta => douta
        );


end architecture behavior;

