Tolerating Cache-Miss Latency with Multipass Pipelines

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Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu

Published: 01 Jan 2006, Last Modified: 14 Nov 2024IEEE Micro 2006EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.