VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

Patrick Yubeaton, Andre Nakkab, Weihua Xiao, Luca Collini, Ramesh Karri, Chinmay Hegde, Siddharth Garg

Keywords: verilog, dataset generation, formal verification, reasoning

TL;DR: We present VeriThoughts, a dataset for reasoning-based Verilog Code generation; we also present a new benchmark based on formal verification, and a suite of small-scale models specialized for Verilog generation.

Abstract: This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees.

Dataset URL: https://huggingface.co/collections/wilyub/verithoughts-datasets-6826de76e798014f05de6c0f

Code URL: https://github.com/wilyub/VeriThoughts

Primary Area: Datasets & Benchmarks for applications in language modeling and vision language modeling

Submission Number: 1355