Mapping dynamic programming onto a linear systolic array

V. K. Prasanna Kumar, Yu-Chen Tsai

Abstract: In the paper we show a single, efficient implementation of dynamic programming on alinear array using a new mapping methodology. In this method, we start with a known 2-D array onto which the dynamic programming algorithm has been mapped. By partitioning and stretching, this 2-D array is mapped onto a linear array. We derive a data movement scheme to simulate the data streams and the computations in the 2-D array. This scheme is implemented usingfast/slow data channels. Compared to known designs in the literature our design uses constant storage in each PE, constant number of I/O lines and continuous I/O sequence. Besides, the data and control flow in the array is unidirectional. This property makes the design suitable for implementation on the well-known fault-tolerant Wafer Scale Integration model.