HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation

Antian Wang, Weihang Tan, Zhenyu Xu, Tao Wei, Caiwen Ding, Keshab K. Parhi, Yingjie Lao

Abstract: Homomorphic encryption enables computations on the ciphertext to preserve data privacy with significant computational overhead compared to plaintext computations. In response to this challenge, we present HEDWIG, a novel end-to-end hardware acceleration system designed to enhance the efficiency of homomorphic encryption, specifically tailored for the latest BFV-HPS scheme. To the best of our knowledge, this is the first hardware accelerator for the BFV-HPS scheme variant. Key contributions include computation workload reduction via approximation, hardware resource optimization on modular computation modules, and computation workflow optimization to improve HE algorithm efficiency. The proposed HEDWIG is employed to perform homomorphic evaluations over machine learning model inference with a high reduction in DSP usage compared to prior BFV RNS variants FPGA accelerator with clock frequency reached 300MHz.