Abstract: Efficient representation of sparse matrices is critical for reducing memory usage and improving performance in hardware-accelerated computing systems. This letter presents memory-efficient delta-compressed storage row (MdCSR), a novel sparse matrix format designed to improve both storage efficiency and execution speed. MdCSR replaces absolute column indices with compact relative offsets and selectively applies delta encoding, resulting in a more compact index structure. Compared to traditional formats, it achieves an average of 15.45% memory savings over compressed sparse row (CSR), 52.77% over dCSR, and around 20% reduction in execution time. A dedicated architecture for CSR to MdCSR compression is also presented, optimized for real-time and low-overhead FPGA deployment.
External IDs:dblp:journals/esl/GSKUK25
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