Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits

Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan

Abstract: Matching pursuit (MP) algorithm is popularly used as a low-cost alternative to the orthogonal matching pursuit (OMP) algorithm for the reconstruction of signal from compressively sensed samples. In this paper, we have proposed an efficient scheduling of computation along with a novel reconfigurable inner-product (IP) unit and buffer units to provide regular inflow of input, and storage of intermediate results for efficient implementation of MP algorithm. The proposed reconfigurable IP unit can compute inner-products of different lengths by reusing the arithmetic components with very low reconfiguration overhead. We have customized on-chip buffers to exploit desired level of parallelism with lower latency and higher hardware utilization efficiency. The proposed structure of MP algorithm for the reconstruction of compressively sensed data is found to involve nearly 15% less critical path delay, 7% less area, 10% less reconstruction time, and 17% less area-delay-product (ADP) than the existing structure.