Verification and Test

Jörg Henkel

Abstract: fig orientation="portrait" position="float" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <graphic orientation="portrait" position="float" xlink:href="henke-2737530.tif"/> </fig> This issue is focused on the special issue on “Emerging Challenges and Solutions in SoC Verification” from Guest Editors Magdy Abadir, Jayanta Bhadra, Wen Chen, and Li-C Wang. This special issue on verification is very timely, as new developments demand new verification techniques. For instance, the increasing heterogeneity of on-chip-systems (mainly to increase the power end energy efficiency; see also <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Design&amp;Test</i> issue on Dark Silicon, <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7862860&amp;punumber=6221038</uri> ) makes verification more complex. Also, the newest trends in application, such as Internet-of-Things, require new verification approaches. The guest editors also present an article on “Challenges and Trends in Modern SoC Design Verification” to round up this interesting special issue. Many thanks to our guest editors for bringing the newest developments to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Design&amp;Test</i> .