An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics

Georgios Chatzianastasiou, George A. Constantinides

Abstract: One of the most heavily used kernels of many ray tracing algorithms is the intersection test for a ray with an Axis-Aligned Bounding Box (AABB). Floating point imprecision leads to incorrect ray/AABB intersection test results, which can lead not only to a substantial error in the photorealism of the image during rendering, by producing visually objectionable holes (false misses), but also to significant penalties to the ray tracer's performance and the power consumed, since the traversal is unnecessary (false hits). This work suggests a novel architecture that uses carefully-designed directed rounding and intervals for eliminating false misses and for investigating the trade-offs between false hit error rate, area and throughput when downscaling from high precision to low precision. The flexibility of FPGAs in terms of computational structure, pipelining and parallelism in conjunction with the massively parallel floating point operations in ray/AABB tests, makes them a very efficient choice for custom precision hardware computation. A fully-pipelined high-throughput architecture designed in RTL is demonstrated, featuring the provable elimination of false misses while quantifying false hits.