Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study

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Ásgeir Th. Eiríksson, Kenneth L. McMillan

Published: 1995, Last Modified: 05 Nov 2025CAV 1995EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: We present a case study of the use of formal verification methods in a computer system design project. The SMV model checker was integrated into the project design flow, and used to verify a specification of a cache coherency protocol for a directory based, distributed shared memory, machine. Both the processor and I/O portions of the protocol specification were verified, within the strict time schedule of the overall project.