Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution

Shibing Mo, Jing Liu, Jianchu Xu, Ruilin Wu

TL;DR: OrderPlace leverages proxy-guided LLM evolution to discover superior macro placement sequences, cutting wirelength by 34% vs WireMask-EA and 14% vs EGPlace on ISPD 2005 benchmarks by optimizing the critical sequencing dimension.

Abstract: Macro placement is a fundamental step in modern VLSI physical design, determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics. In this work, we demonstrate that the placement sequence is not merely a preprocessing step but a decisive factor in optimization, where suboptimal early decisions trigger irreversible domino effects that constrain the solution space. To harness this unexplored dimension, we propose \textbf{OrderPlace}, a novel framework that automates the discovery of macro placement strategies via proxy-guided Large Language Model (LLM) evolution. Unlike existing methods that rely on manual rules like area or connectivity, OrderPlace leverages LLMs to evolve generalizable, code-level ordering strategies—ranging from static metrics to dynamic, physics-inspired mechanisms. To mitigate the prohibitive cost of evaluating sequences, we introduce a lightweight proxy evaluation mechanism that efficiently filters candidates using a deterministic greedy probe. Experimental results on the standard ISPD 2005 benchmarks demonstrate that OrderPlace discovers novel ordering strategies. Compared with WireMask-EA and the state-of-the-art method EGPlace, OrderPlace reduces wirelength by 34.04% and 14.08%, respectively.

Lay Summary:

Designing a modern chip requires placing many large circuit blocks, called macros, onto a limited chip area. The quality of this placement strongly affects the final chip performance, especially the total wirelength needed to connect the blocks. Most existing methods focus on deciding where each block should go, while using simple fixed rules to decide the order in which blocks are placed.

In this paper, we show that the placement order is itself a key design choice. A poor early decision can limit the options for later blocks and cause a chain reaction that leads to a worse placement. To address this, we propose OrderPlace, a framework that uses large language models to automatically discover better ordering strategies. These strategies are written as code and can go beyond standard human-designed rules.

Because testing every possible order with a full placement run is too expensive, OrderPlace uses a fast approximate evaluation step to filter promising strategies. Experiments on standard chip design benchmarks show that the discovered ordering strategies reduce wirelength compared with strong existing methods, demonstrating that optimizing placement order is a practical way to improve chip placement quality.

Primary Area: Applications

Keywords: Macro Placement, Chip design, Automatic Algorithm Design，Sorting Algorithm

Submission Number: 12180