Internal I/O Testing: Definition and a Solution

Sreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim

Abstract: Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.