Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping

Yichuan Bai, Zhuang Shao, Chenshuo Zhang, Aojie Jiang, Yuan Du, Li Du

Abstract: This demonstration showcases an efficient neural network processor implemented in TSMC 28nm CMOS technology. The processor conducts neural network inference with 16-bit dynamic fix-point activation and 10-bit dynamic fix-point weight. The reconfigurable streaming architecture is employed for off-chip data transmission reduction and on-chip shortcut mapping. An integrated neural network toolchain, including network model converter, quantitative analysis tool, and deep learning compiler, is also developed for fast network deployment.