ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA

Pankaj Bhowmik, Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda

Published: 2021, Last Modified: 27 Feb 2026FCCM 2021EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: This paper presents an event-based split-CNN architecture (ESCA) for running time-critical vision applications with comparatively less memory footprint while consuming low power. ESCA has a dedicated hardware architecture and scheduling of on-chip memory buffering using a split-CNN that reduces memory requirements by splitting the feature maps into small patches and independently executes them. The model emulates the concepts of the biological vision system to obtain possible events from each patch. We save energy and time by processing only the patches with possible events. The data-level parallelism is employed with a deep pipeline strategy that accelerates the system. We implement the design in the Virtex UltraScale+ FPGA at 320 MHz. Simulation results show that the architecture obtains significant speedup while power-saving depends on each image patch’s features.
Loading