Live Demo: Memory-Efficient Hardware Design for a Real-Time Convolutional Encoder-Decoder Network

Min-Wu Jeong, Chanyong Shin, Chae-Eun Rhee

Abstract: This work presents a FPGA-based convolutional-neural-network (CNN)-based encoder-decoder accelerator for interpolation of high-resolution images. The baseline model is DVF [1]. The proposed system is demonstrated on Virtex UltraScale+ HBM VCU128 evaluation kit.