Zhengyu Chen

Joined

May 2023

Names

Zhengyu Chen (Preferred)

Emails

****@u.northwestern.edu (Confirmed)

****@samabnovasystems.com

****@cornell.edu

Personal Links

Google Scholar

DBLP

ORCID

Career & Education History

Principal Researcher

Sambanova Systems (sambanovasystems.ai)

2020 – 2023

PhD student

Northwestern University, Northwestern University (u.northwestern.edu)

2015 – 2020

MS student

Cornell University (cornell.edu)

2013 – 2015

Advisors, Relations & Conflicts

PhD Advisor

Jie Gu

2015 – 2020

Expertise

NLP

LLM

code generation

2018 – 2023

Generative adversarial network

2018 – 2023

VLSI AI chip design

2013 – 2023

Publications

On the Tool Manipulation Capability of Open-sourced Large Language Models
Qiantong Xu, Fenglu Hong, Bo Li, Changran Hu, Zhengyu Chen, Jian Zhang
- FMDM@NeurIPS2023
- Readers: Everyone
On the Tool Manipulation Capability of Open-sourced Large Language Models
Qiantong Xu, Fenglu Hong, Bo Li, Changran Hu, Zhengyu Chen, Jian Zhang
- Submitted to ICLR 2024
- Readers: Everyone
PIE: Simulating Disease Progression via Progressive Image Editing
Kaizhao Liang, Xu Cao, Kuei-Da Liao, Tianren Gao, Wenqian Ye, Zhengyu Chen, Jianguo Cao, Tejas Nama, Jimeng Sun
- Submitted to ICLR 2024
- Readers: Everyone
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency
Zhengyu Chen, Xi Chen, Jie Gu
- Published: 01 Jan 2021, Last Modified: 12 May 2023
- ISSCC 2021
- Readers: Everyone
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing
Zhengyu Chen, Jie Gu
- Published: 01 Jan 2021, Last Modified: 12 May 2023
- IEEE J. Solid State Circuits 2021
- Readers: Everyone
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices
Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu
- Published: 01 Jan 2020, Last Modified: 12 May 2023
- VLSI Circuits 2020
- Readers: Everyone
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation
Zhengyu Chen, Jie Gu
- Published: 01 Jan 2019, Last Modified: 12 May 2023
- IEEE J. Solid State Circuits 2019
- Readers: Everyone
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction
Zhengyu Chen, Hai Zhou, Jie Gu
- Published: 01 Jan 2019, Last Modified: 12 May 2023
- IEEE Trans. Very Large Scale Integr. Syst. 2019
- Readers: Everyone
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput
Zhengyu Chen, Jie Gu
- Published: 01 Jan 2019, Last Modified: 12 May 2023
- ISSCC 2019
- Readers: Everyone
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing
Zhengyu Chen, Hai Zhou, Jie Gu
- Published: 01 Jan 2019, Last Modified: 12 May 2023
- DAC 2019
- Readers: Everyone

View all 14 publications