A Dataflow-Aware Network-on-Interposer for CNN Inferencing in the Presence of Defective Chiplets

Harsh Sharma, Ümit Y. Ogras, Ananth Kalyanaraman, Partha Pratim Pande

Abstract: The emergence of 2.5D chiplet platforms provides a new avenue for compact scale-out implementations of deep learning (DL) workloads (WLs). Integrating multiple small chiplets using a network-on-interposer (NoI) offers not only significant cost reduction and higher manufacturing yield than 2-D ICs but also better energy efficiency and performance. However, defects in chiplets may compromise performance since they restrict the computing capability. Therefore, carefully designed chiplet and NoI link placement, and task mapping schemes, in presence of defects, are necessary. In this article, we propose a defect-aware NoI design approach using a custom-defined space-filling curve (SFC) for efficient execution of mixed WLs of convolutional neural network (CNN) inference tasks. We demonstrate that the k-ary n-cube-based NoI topologies can be degenerated into SFC-based counterparts, which we refer to as SFCed NoI topologies. They enable high performance and energy efficiency with lower fabrication costs over their parent k-ary n-cube counterparts. The SFCed approach helps us to extract high performance from an inherently defective system. We demonstrate that SFCed design achieves up to $2.3\times $ and $3.5\times $ reduction in latency and energy, respectively, compared to parent NoI architectures while executing diverse DL WLs.

External IDs:dblp:journals/tcad/SharmaOKP24