D-PIFO: A Dynamic Priority Scheduling Algorithm for Performance-Critical Packets Based on the Programmable Data Plane

Jialu Cui, Junxing Zhang

Abstract: Traffic scheduling is critical to ensuring that the switch meets required quality of service and performance goals. Existing research on traffic scheduling to improve network service quality either has few integrated circuit (ASIC) hardware implementations for switch applications or requires multiple very strict priorities. Packet scheduling has the advantage of fine control in network communications, ensuring that critical data packets or real-time data can be transmitted in a timely manner. Although the traditional fixed hardware packet scheduling method can achieve effective packet forwarding, it lacks flexibility and scalability. The emerging of the programming protocol-independent packet processor (P4) can program the scheduling algorithm into the data plane without changing the hardware, allowing users to customize packet scheduling rules according to their own needs. It can avoid resource waste, use remaining resources where users need them, and achieve a more flexible, efficient, and scalable network architecture. This paper proposes a packet scheduling algorithm implemented under the programmable data plane framework, namely Dynamic Push-In-First-Out (D-PIFO). The algorithm consists of three components: packet admission control sub-algorithm, packet sorting and priority queue adaptive mapping sub-algorithm, and intelligent queue selection strategy under different loads. The goal of this paper is to ensure that all types of traffic receive acceptable service levels while meeting strict targets for critical traffic. Simulation results demonstrate the superiority of this algorithm over existing work.