Secure and Scalable TLB Partitioning Against Timing Side-Channel Attacks

Tianyi Huang, Xiaolin Zhang, Kailun Qin, Boshi Yuan, Chenghao Chen, Yipeng Shi, Chi Zhang, Dawu Gu

Abstract: Modern micro-architectural attacks, including cache-based side-channel and speculative execution attacks, have increasingly challenged the security of contemporary processors. Recent studies have revealed that the Translation Lookaside Buffer (TLB) can also serve as a vector for timing-based side-channel and covert channel attacks, exposing sensitive information similarly to cache-based attacks. As TLBs are crucial to both CPUs and GPUs, the prevalence and potential impact of such attacks are likely to increase. However, existing defenses often fail to balance security guarantees with architectural scalability, particularly under realistic multi-process execution environments.

External IDs:dblp:conf/icics/HuangZQYCSZG25