Efficient Cell-Aware Defect Characterization for Multi-bit Cells

Ruifeng Guo, Brian Archer, Kevin Chau, Xiaolei Cai

Abstract: Cell-aware test is used to improve test quality and diagnosis accuracy. Simulation based cell-aware test model generation is a time consuming process. The overall characterization runtime of a standard cell is generally a function of pin count and the number of SPICE level devices. Exhaustive defect analysis requires unique simulations for each defect site across all cells in a library. Multi-bit cells have been widely adopted in low-power designs and they usually have both a large number of inputs, and SPICE level devices. This paper presents a general flow for cell-aware test model generation for clarity. We then propose a technique to speed-up the cell-aware defect model generation for multi-bit cells. Our evaluation on 16nm library cells shows the effectiveness of the proposed technique.