A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications

Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

Abstract: This work presents an energy-efficient CIM-CAM processor for both neural network (NN) and recommendation system (RecSys) applications. The main contributions include: 1) A reconfigurable Zig-Zag memory access architecture for diverse convolution/MVM to minimize SRAM access; 2) A backbone-systolic CIM array towards a higher system/macro efficiency ratio; 3) A distribution-aware block/self-gating (DABG) CAM to reduce both off-chip access and on-chip search power for the memory-dominate embedding layer. The fabricated 28nm chip demonstrates 37.9-81.5TOPS/W system energy efficiency for NN and 12.3-56.1nJ/request for RecSys. This work achieves $2.4\times/3.6\times$ energy/area efficiency for NN and $370\times$ energy reduction for RecSys compared with the state-of-the-art.