A novel test compression algorithm for analog circuits to decrease production costs

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Abstract: Highlights•Our approach compresses tests automatically by using an optimality objective. We formulate the test compression problem as the optimization of a functional over the transient response of the circuit and prove its correctness. Our technique can reduce the test time by 94%.•We propose a new optimization algorithm using random trees to optimize the objective function. Our technique works for nonlinear and CMOS circuits.•We propose a greedy algorithm to compress tests in the presence of process variation.•Our algorithm has a parallel version that increases the efficiency of the algorithm.

External IDs:dblp:journals/integration/AhmadyanNV17