Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level Synthesis

Richard C. Yarnell, Mousam Hossain, Raul Graterol, Ayush Pindoria, Sujan Ghimire, Muhtasim Alam Chowdhury, Soheil Salehi, Yu Bai, Ronald F. DeMara

Abstract: There is significant demand and urgency to prepare electrical and computer engineering students regarding the operational and performance characteristics of machine learning (ML) hardware accelerators. Convolutional Neural Networks (CNNs), which are utilized for real-time and large dataset image classification tasks, are appropriate targets for hardware acceleration. Designing accelerators for CNNs necessitates understanding the manipulation of CNN parameters. We introduce a hands-on pedagogy whereby learners can identify, modify, and appreciate the interaction of the CNN parameters within an interactive GUI. CASCADE (Computer Aided Student's CNN Analyzer for Design Exploration), a simulation-based framework for Design Space Exploration (DSE) of CNN FPGA-based accelerators is developed, including datapath synthesis, simulation, training, and testbench steps. We offer a case study of High-Level Synthesis (HLS) based CNN implementations targeting the MNIST dataset and present simulation results, namely hardware utilization, accuracy, and operating frequency, and offer insight into potential design trade-offs facing modern engineers.