Incorporating Compiler Optimization in Software Estimation for FPGA-based Embedded Processors

Deshya Wijesundera, Thilina Perera, Dilina Dehigama, Thambipillai Srikanthan

Abstract: The embedded processors beside the traditional FPGA fabric in FPGA-based System-on-Chip (SoC) devices make them an attractive alternative for realizing the software portions of the application while using the FPGA fabric for hardware acceleration. Traditional performance evaluation of applications on these embedded processors require design expertise and costly commercial tools or hardware for each processor. Thus, software based performance estimation techniques that eliminate these requirements are considered a viable alternative. However, estimation techniques which can be applied across different embedded processors do not account for compiler optimizations. This paper proposes a framework for software estimation of embedded processors that incorporates compiler optimizations. The proposed technique relies on a neural network estimation model instead of FPGA synthesis and execution-based techniques, that necessitates costly commercial tools and hardware, and does not require design expertise. Experimental evaluations on the Intel Nios II processor show an average accuracy of 92.5% with a R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> value of 0.9977 for the neural network, which highlights the suitability of the proposed technique.