microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware

Dewei Wang, Jonghyun Oh, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok

Abstract: We present an ultra-low-power automatic speech recognition (ASR) accelerator in 28nm. We have developed a bio-inspired neuron model with per-neuron trainable decay rates and thresholds. The ASR recurrent neural network, designed with the neuron model, requires $\sim$4X less weights than LSTM to achieve the same accuracy. We also created a digital 6T-SRAM-based compute-in-memory (DCIM) macro. The ASR accelerator leverages the DCIM’s high computing throughput to reduce the required clock frequency and supply voltage, thereby reducing the power consumption to $32\mu \mathrm{W}$ at the competitive inference accuracy on the TIMIT ASR benchmark.