Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology

Johann Knechtel, Tarek Ashraf, Natascha Fernengel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Ozgur Sinanoglu, Hussam Amrouch

Abstract: Highlights•We study design-time technology evaluation for power side-channel attacks (PSCAs).•We focus on industrial-grade 14 nm fin field-effect transistor (FinFET) technology.•We use device-level measurement data from Intel high-volume manufacturing nodes.•We build up accordingly well-characterized standard-cell libraries.•We utilize a commercial-grade computer-aided design flow for PSCA evaluation.•We study voltage switching as countermeasure against correlation power analysis (CPA).•Resilience against CPA increases the more we switch, the larger the voltage difference.•But, information leakage is increasing for such configurations as well.•Thus, careful study of voltage differences, switching ratios is required.•Such study requires technology-accurate design-time evaluation, as proposed here.•Our findings are robust: we conduct batches of randomized-but-reproducible CPA runs.•Our findings are conservative: we use technology-accurate, zero-delay simulations.•Our findings serve as guidelines for secure design, e.g., for key refresh rates.