A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor

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Marcello M. Muñoz, Denis Maass, Murilo Perleberg, Luciano Agostini, Guilherme Corrêa, Marcelo Porto

Published: 01 Jan 2025, Last Modified: 27 Feb 2026IEEE Design & TestEveryoneRevisionsCC BY-SA 4.0
Abstract: Editor’s notes: This article proposes a specialized hardware architecture for the VVC affine motion estimation reconstructor. The design aims to maintain high coding efficiency while enabling real-time processing of UHD video. —Ney Calazans, Federal University of Santa Catarina (UFSC), Brazil —Bruno Zatt, Federal University of Pelotas (UFPel), Brazil