A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC

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Sewon Lee, Hyein Kang, Minjae Lee

Published: 2025, Last Modified: 26 Jan 2026IEEE J. Solid State Circuits 2025EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: This article presents a compact 13-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) designed to enhance energy efficiency under various comparator input common-mode voltage scenarios. The proposed comparator structure features a complementary split pre-amplifier to extend the input common-mode range, resulting in an SNDR drop of approximately 1 dB even at a near 0-V ADC input common-mode voltage of 0.038 V. Furthermore, the proposed grounded-finger capacitive digital-to-analog converter (CDAC) reduces the impact of hard-to-scale fringe capacitance with a regular structure in order to reduce the number of CDAC elements and area. Utilizing these techniques, the prototype SAR ADC implemented in a 65-nm CMOS LP process achieves an uncalibrated integral non-linearity (INL) of 1.07 LSB, an 87.4% reduction in elements, and 70.6-dB SNDR in a 0.0372 mm2, consuming only $15.1~{\mu }$ W at 0.75 V that results in a Walden figure of merit (FoMW) of 2.72 fJ/conversion-step.