Lightweight Forth Programmable NoCs

Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar

Abstract: Designing around packet-switching networks-onchip (NoCs) has been an increasingly popular architecture paradigm for distributed on-chip computing. The availability of highly configurable and synthesizable NoC generators, such as CONNECT, has freed designers to focus instead on application mapping and other aspects of this design paradigm. In conventional NoCs, routers throughout the network are all uniformly provisioned with dedicated resources (e.g. crossbar switches, virtual-channels, arbiters) so as to route data as quickly as possible while keeping average message deliver times low. Many applications however, may not be sensitive to these metrics, and may otherwise have needs that may not be readily supported, or may present opportunities to simplify routers. We present a configurable synthesizable NoC generator with programmable routers built around lightweight Forth cores. The use of programmable routers in onchip networks opens up interesting possibilities for applications, and this notion, at least in the lightweight category, has never been explored. For illustration, support for features such as broadcast and multicast, adaptive routing, and systolic array computing have been implemented through programming the routers. The approach has been evaluated through a comparison in terms of network performance characterization and resource overhead.