LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection

Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia

Abstract: Due to the globalization of the semiconductor supply chain and the adoption of the zero trust model, hardware Trojan attacks pose significant security threats introduced by untrusted entities. Hardware Trojans relate to malicious modification of a design before fabrication, resulting in unintended functional or side-channel behavior, such as causing a Denial of Service (DoS) attack or leaking sensitive information. Detecting hardware Trojans in fabricated silicon chips is extremely challenging primarily due to the vast possible attack space. Directed test generation towards activation (i.e., trigger) and/or manifestation (e.g., observation of payload) of the viable Trojans with conventional post-manufacturing Automatic Test Pattern Generation (ATPG) process is known to be practically infeasible. Hence, researchers have explored statistical test techniques for detecting arbitrary instances of Trojan attacks through post-silicon functional testing. However, existing statistical test solutions lack in effective trigger and payload coverage and suffer from scalability issues. In this paper, we propose LATENT, a scalable payload-aware statistical test pattern generation technique for high-coverage Trojan detection leveraging the power of existing functional ATPG solutions. Our experimental study on large population of randomly inserted Trojans in a suite of open-source designs shows promising results in both trigger and Trojan coverage.