Abstract: Successive-approximation register (SAR) ADCs are susceptible to non-linearities due to capacitor mismatch. This brief proposes a transition points-based calibration of the SAR ADC using an RC-filtered square wave by looking at the histogram of output digital codes to improve the linearity without any additional analog circuitry. The proposed method is validated with an $\mathbf {8}$ -bit SAR ADC fabricated in UMC $\mathbf {180}$ -nm CMOS. The proposed calibration algorithm improves the signal-to-noise and distortion ratio (SNDR) of the $\mathbf {8}$ -bit ADC from $\mathbf {42.87}$ dB to $\mathbf {46.91}$ dB, and the spurious-free dynamic range (SFDR) from $\mathbf {51.95}$ dB to $\mathbf {60.61}$ dB.
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