A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications

Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha

Abstract: Binarized convolutional neural network (BCNN) is a promising and efficient technique toward the landscape of Artificial Intelligence of Things (AIoT) applications. In-Memory Computing (IMC) has widely been studied to accelerate the inference task of BCNN to maximize both throughput and energy efficiency. However, existing IMC circuits and architectures are only optimized for a fixed kernel size and nominal voltage operation, which poses practical limitations on optimal network architecture exploration and additional energy efficiency benefits. In this brief, we present a reconfigurable, near-threshold IMC-based BCNN accelerator design. The IMC-based accelerator architecture is scalable for different kernels sizes ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \times 3 \times d$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \times 5 \times d$ </tex-math></inline-formula> ) and achieves high resource utilization for both cases. Moreover, the IMC bitcell is optimized for reliable near-threshold operation. Implemented in a 55-nm CMOS process, our proposed reconfigurable IMC-based BCNN accelerator achieves 5526 TOPS/W energy efficiency at 0.4V, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.38\times $ </tex-math></inline-formula> higher compared to the state-of-the-art designs. The inference accuracies of our proposed design are 97.73%, 82.56%, and 92.61% across three datasets (MNIST, CIFAR-10, and SVHN), respectively.