FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Shien Zhu, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu

Abstract: Convolutional neural networks (CNNs) demonstrate excellent performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, binary and ternary weight networks (BWNs and TWNs) have a unique advantage over 8 and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favored on in-memory-computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity than BWNs, IMC acceleration for TWNs has limited research. TWNs on the existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient. In this article, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a sparse addition control unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory sense amplifier (SA) to avoid the time overhead of both carry propagation and writing back the carry to memory cells. Third, we further propose a combined-stationary data mapping to reduce the data movement of activations and weights and increase the parallelism across memory columns. Simulation results show that for addition operations at the SA level, FAT achieves $2.00\times $ speedup, $1.22\times $ power efficiency, and $1.22\times $ area efficiency compared with a state-of-the-art IMC accelerator ParaPIM. FAT achieves $10.02\times $ speedup and $12.19\times $ energy efficiency compared with ParaPIM on networks with 80% average sparsity.