Compiler Support for Software Cache Coherence

Sanket Tavarageri, Wooil Kim, Josep Torrellas, P. Sadayappan

Abstract: The advent of multi-core processors with a large number of cores and heterogeneous architecture poses challenges for achieving scalable cache coherence. Several recent research efforts have focused on simplifying or abandoning hardware cache coherence protocols. However, this adds a significant burden on the programmer, unless automated compiler support is developed. In this paper, we develop compiler support for parallel systems that delegate the task of maintaining cache coherence to software. Algorithms to automatically insert software cache coherence instructions into parallel applications are presented. This frees the programmer from having to manually insert coherence annotations, which can be tedious and error-prone. Experimental evaluation over a number of benchmarks demonstrates that effective compiler techniques can make software cache coherence competitive with hardware coherence schemes both in terms of energy and performance.