An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOX

Kyungmi Kim, Soeun Choi, Eunkyeol Hong, Yoonseo Jang, Jaehyeong Sim

Abstract: This paper presents a hardware accelerator for YOLOX, the popular object detection convolutional neural network (CNN) model. It features a novel 1D systolic adder trees (SATs) to efficiently handle 1 1 or 3 3 convolution. The corresponding data feeding logic is designed to provide activations seamlessly to SAT. Evaluation results performed on Nangate 45nm process show that the proposed accelerator achieves higher area and energy efficiency compared to the previous YOLOX accelerator.