A 32.5mW Mixed-Signal Processing-in-Memory-Based k-SAT Solver in 65nm CMOS with 74.0% Solvability for 3D-Variable 126-Clause 3-SAT Problems

Daehyun Kim, Nael Mizanur Rahman, Saibal Mukhopadhyay

Abstract: Boolean satisfiability (k-SAT, k ≥3) is an NP-complete combinatorial optimization problem (COP) with applications in communication, flight network, supply chain and finance, to name a few. The ASICs for SAT and other COP solvers have been demonstrated using continuous-time dynamics [1], simulated annealing [2], oscillator interaction [3] and stochastic automata annealing [4]. However, prior designs show low solvability for complex problems ([1] shows 16% solvability for 30 variables and 126 clauses), and use a small, fixed network topology (King's graph [3] or Lattice Graph [2] or 3-SAT [1]) limiting the flexibility of problem solving. A digital fully connected processor enables flexibility but incurs a large area, latency and power overhead [4]. This paper presents a k-SAT solver where a Continuous-Time Stochastic Recurrent Neural Network (CT-SRNN), controlled by a Discrete-Time Finite-State-Machine (DT-FSM), uses unsupervised learning to search for an optimal solution (Fig. 29.1.1). A 65nm test-chip based on a Mixed-Signal Processing-in-Memory (MS-PIM) architecture is presented. Measured results demonstrate a higher solvability (74.0% for 30 variables and 126 clauses, vs. 16% in [1]) and an improved flexibility (k > 3, different number of variables per clause) in mapping k-SAT problems.