Constrained Floorplanning with Whitespace

Published: 01 Jan 2004, Last Modified: 06 Aug 2024VLSI Design 2004EveryoneRevisionsBibTeXCC BY-SA 4.0
Abstract: This paper considers the constrained floorplanning problem in the context of a design scenario where floor-plans are required to contain some white space to facilitate subsequent buffer insertion. An elegant bounded iterative methodology for floorplan-refinement based on the min-cost max-flow formulation of Feng et al augmented by a heuristic area-redistribution algorithm is presented. This approach results in substantially better quality floorplans than previously reported as substantiated by our experimental results.
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