Efficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation Acceleration

Jiahao Xu, Chunyan Pei, Shengbo Tong, Wenjian Yu

Abstract: As the scale of integrated circuit (IC) design continues to expand, the multi-FPGA system (MFS) is widely employed for logic emulation and simulation acceleration which ensures the functional correctness of logic circuits. During this process, circuit partitioning becomes a dispensable step. In this work, we address the hypergraph modeling techniques for the MFS-orientated circuit partitioning. Firstly, an efficient adaptive flattening algorithm considering multi-dimensional resource constraints and based on dynamic programming (DP) is proposed. Then, a parallel algorithm for clock modeling is proposed. With them, an efficient tool of hypergraph modeling is developed. Experiments on industrial benchmarks with up to sixty million cells have validated the efficiency and correctness of the proposed techniques. The results also demonstrate the benefit of the adaptive flattening to the subsequent hypergraph partitioning, and the significant acceleration effects of the proposed DP-based adaptive flattening and the parallel clock modeling algorithms.