Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers

Ailing Piao, Aili Wang, C.-J. Richard Shi

Abstract: A 12-bit 8-wire 8-level (12B8W8L) permutation coding scheme is designed for high speed parallel I/O interfaces. The proposed 12B8W8L permutation coding scheme improves pin efficiency to 150%, compared to 50% pin efficiency of the non-return-to-zero (NRZ) signaling, while keeping the encoding and decoding logic simple. It reduces the baud rate to 1/3 of NRZ signaling compensating for reduced SNR. The proposed coding scheme eliminates simultaneous switching noise (SSN) and reference voltage noise. A prototype transceiver is designed, simulated and verified in a 65 nm CMOS process, achieving 6 Gb/s/pin data rate and 0.99 pJ/bit energy efficiency over 4-inch FR4 channels.