A Real-time Super-resolution Accelerator Using a big. LITTLE Core Architecture

Xuan Truong Nguyen, Tuan Nghia Nguyen, Hyuk-Jae Lee, Kyujoong Lee

Abstract: Image super-resolution (SR) networks have shown a remarkable restoration performance but come with a huge memory bandwidth requirement due to a large-size input and lack of a pooling layer. As a result, SR accelerators usually adopted a streaming-like scheme to fit a highly customized and small SR network to available resources, which causes a large accuracy drop. To address this problem, this work proposes an SR accelerator using a big.LITTLE core architecture which is able to execute various networks in real-time. The proposed SR processor achieves an inference speed of 36.63 frames per second and a throughput of 221.79 GOPs at 200MHz for ×2 SR (from 960×540 to 1920×1080) while using only 1,280 eight-bit multipliers and 330 KB on-chip SRAM.