A ferroelectric memory-based secure dynamically programmable gate array

Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima

Abstract: A nonvolatile ferroelectric memory-based eight-context dynamically programmable gate array (DPGA) enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories as well as the multicontext architecture. Since read and program sequences of configuration data loading from/to the DPGA are securely protected, unauthorized users cannot access the stored configuration data. The associated configuration memory consists of a SRAM-based six-transistor and 4-ferroelectric capacitor cell. The developed configuration memory achieves access time of 4ns, comparable to standard SRAM, which is 20 times faster than conventional ferroelectric memory; furthermore, it features a nondestructive read operation and a stable data recall scheme. The employed logic block circuit can effectively improve the available number of logic gates for the multicontext scheme with minimum area overhead. The prototype nonvolatile DPGA is fabricated in a 0.35-μm CMOS with ferroelectric memory technology, and the implementation result of the Data Encryption Standard (DES) encryption/decryption functions on this DPGA presents proper operation up to 51 MHz at 3.3V. The nonvolatile storage of configuration memory is verified for power-supply voltage as low as 1.5 V at room temperature, which is the lowest operation voltage ever reported for PbZrTiO3 (PZT)-based ferroelectric memories.