Time redundancy and gate sizing soft error-tolerant based adder design

Aiman H. El-Maleh, Ghashmi H. Bin Talib

Abstract: Highlights•An efficient soft error tolerance approach for arithmetic circuits is proposed with high performance and low area overhead.•It is based on exploiting time redundancy and gate sizing using C-element.•It takes advantage of the varying and increasing delay across outputs to assign varying delay element sizes.•Compared to TMR, the technique achieves a 42% area overhead reduction and a 5% delay reduction in a 64-bit adder case.•It has the advantage of being able to design fault tolerant circuits with any desired performance level.•Hence, it provides the desired level of performance-area trade-off.