High-Speed and Ultra-Energy-Efficient In-Memory Computing Circuit for ADMM-Based Box-Constrained Massive MIMO Signal Detection

Jia-Hui Bi, Shaoshi Yang, Ping Zhang

Abstract: The emerging memristor-array-based in-memory computing (IMC) technology enables high-speed, energy-efficient matrix operations, offering a new paradigm for high-dimensional matrix computing tasks, such as signal detection in massive multiple-input multiple-output (MIMO) systems. Memristor arrays have been applied to linear and maximum-likelihood detection, but applying them to other detection algorithms remains a challenge. In this letter we propose an IMC circuit for box-constrained signal detection based on the alternating direction method of multipliers (ADMM). The proposed circuit consists of three subcircuits that collaboratively perform a single ADMM iteration through analog computation. The impact of memristor conductance errors on the detection performance of the proposed circuit is analyzed, and a countermeasure is proposed. We show that the computational speed and the computational energy efficiency of the proposed circuit are 1.53 times and 64.8 times as high as those of the powerful commercial field-programmable gate array (FPGA) Intel Stratix 10 TX 2800, respectively, while occupying only 4.7% of the FPGA’s package area.

External IDs:dblp:journals/wcl/BiYZ25